[all-commits] [llvm/llvm-project] 7da272: [RISCV][RISCVISelLowering] Add tail agnostic polic...

[Nitin John Raj via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7da272af89f8b4563082eba955ce513e4feff201
      https://github.com/llvm/llvm-project/commit/7da272af89f8b4563082eba955ce513e4feff201
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-03-25 (Sat, 25 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredmax.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredmin.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
    M llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
    M llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll

  Log Message:
  -----------
  [RISCV][RISCVISelLowering] Add tail agnostic policy operand to VECREDUCE instructions

Differential Revision: https://reviews.llvm.org/D146752