[all-commits] [llvm/llvm-project] 51e584: [RISCV][NFC] Renamed [Read/Write]VGather* -> [Read...

[Nitin John Raj via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 51e5846b5645f4a7f6065df1cebaf2842222c180
      https://github.com/llvm/llvm-project/commit/51e5846b5645f4a7f6065df1cebaf2842222c180
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-03-24 (Fri, 24 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV][NFC] Renamed [Read/Write]VGather* -> [Read/Write]VRGatherV*

Differential Revision: https://reviews.llvm.org/D145402


  Commit: 85e0d48a16180bbb3d068e3607c31eb0cbc441ed
      https://github.com/llvm/llvm-project/commit/85e0d48a16180bbb3d068e3607c31eb0cbc441ed
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-03-24 (Fri, 24 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV][NFC] Broke ReadVRGatherVV into ReadVRGatherVV_data and ReadVRGatherVV_index to separate the reads for VRGatherVV

Differential Revision: https://reviews.llvm.org/D145406


  Commit: 08be5e25376dff9a5db34cd583ff82c2b7a8b4d2
      https://github.com/llvm/llvm-project/commit/08be5e25376dff9a5db34cd583ff82c2b7a8b4d2
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-03-24 (Fri, 24 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV][NFC] Added possible SEWs associated with a given LMUL


  Commit: 5a0c27d3719e63c8c4f1a3907ceda2a796e17968
      https://github.com/llvm/llvm-project/commit/5a0c27d3719e63c8c4f1a3907ceda2a796e17968
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-03-24 (Fri, 24 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV][NFC] Remove SEW suffix from pseudoinstructions


  Commit: a075ac05eb59d5bf20508f5048055c09d4db58e5
      https://github.com/llvm/llvm-project/commit/a075ac05eb59d5bf20508f5048055c09d4db58e5
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-03-24 (Fri, 24 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Made vcompress pseudoinstruction SEW-aware


  Commit: 5ab9ae12b703647d2482e71b0a98158ef3a41dea
      https://github.com/llvm/llvm-project/commit/5ab9ae12b703647d2482e71b0a98158ef3a41dea
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-03-24 (Fri, 24 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Made vrgather.vv and vrgatherei16 pseudoinstructions SEW-aware


  Commit: 3cf7e3518072c41757381b1490172c17e57defe4
      https://github.com/llvm/llvm-project/commit/3cf7e3518072c41757381b1490172c17e57defe4
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-03-24 (Fri, 24 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Made division pseudoinstructions SEW-aware


  Commit: 7b39f16fb8845bc9257f03118e50006b943fda32
      https://github.com/llvm/llvm-project/commit/7b39f16fb8845bc9257f03118e50006b943fda32
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-03-24 (Fri, 24 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Made fsqrtv pseudoinstruction SEW-aware


Compare: https://github.com/llvm/llvm-project/compare/1703ff776c3a...7b39f16fb884