[all-commits] [llvm/llvm-project] c0d28d: [AArch64][SME] SelectSMETileSlice should also matc...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c0d28d58fafe4480a129298efb36120170f35fa0
      https://github.com/llvm/llvm-project/commit/c0d28d58fafe4480a129298efb36120170f35fa0
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2023-03-24 (Fri, 24 Mar 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    A llvm/test/CodeGen/AArch64/sme2-intrinsics-select-sme-tileslice.ll

  Log Message:
  -----------
  [AArch64][SME] SelectSMETileSlice should also match to 'reg+0' when slice is ADD with non-constant RHS.

It would decompose an address into a `reg + 0` when the slice was not an ADD,
but when the RHS of the ADD was not a constant, it would simply not match.

This patch fixes that, by always resolving to a `reg + 0` slice.