[all-commits] [llvm/llvm-project] 24847a: [LegalizeTypes][RISCV] Add a special case for (add...

Liao Chunyu via All-commits all-commits at lists.llvm.org
Thu Mar 23 18:45:58 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 24847a90aaf5842041a2cfa977a4167997307b50
  Author: LiaoChunyu <chunyu at iscas.ac.cn>
  Date:   2023-03-24 (Fri, 24 Mar 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
    M llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

  Log Message:
  [LegalizeTypes][RISCV] Add a special case for (add X, -1) to ExpandIntRes_ADDSUB

 On targets without ADDCARRY or ADDE, we need to emit a separate
 SETCC to determine carry from the low half to the high half.
 The high half is calculated by a series of ADDs.

 When RHSLo and RHSHi are -1, without this patch, we get:
   Hi = (add (add LHSHi,(setult Lo, LHSLo), -1)
 Where as with the patch we get:
   Hi = (sub LHSHi, (seteq LHSLo, 0))

 Only RHSLo is -1 we can instead do (setne Lo, 0).

 Similar to gcc: https://godbolt.org/z/M83f6rz39

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D146635

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