[all-commits] [llvm/llvm-project] 84de01: [RISCV] Remove AnyReg RegisterClass used by .insn ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 84de01908b58f3aa25cc3dc700a8a1b01b5263f0
      https://github.com/llvm/llvm-project/commit/84de01908b58f3aa25cc3dc700a8a1b01b5263f0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-03-22 (Wed, 22 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Remove AnyReg RegisterClass used by .insn instructions. Use custom operand instead.

The fake register class interferes too much with the autogenerated
register class tables. Especially the fake spill size.

I'm working on .insn support for compressed instructions and adding
AnyRegC broke CodeGen.