[all-commits] [llvm/llvm-project] 658904: [AArch64] Add asm aliases for MOV, LDR, STR with p...

[CarolineConcatto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 65890469cebb675e9fa0271dc1ab3b1da15df302
      https://github.com/llvm/llvm-project/commit/65890469cebb675e9fa0271dc1ab3b1da15df302
  Author: Caroline Concatto <caroline.concatto at arm.com>
  Date:   2023-03-22 (Wed, 22 Mar 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/MC/AArch64/SVE/pfalse.s
    A llvm/test/MC/AArch64/SVE/predicate-as-counter-aliases.s

  Log Message:
  -----------
  [AArch64] Add asm aliases for MOV, LDR, STR with predicate-as-counter

In the 2022-12 release of the A64 ISA it was updated that the assembler must
also accept predicate-as-counter register names for the source predicate
register and the destination predicate register for:
 * *MOV: Move predicate (unpredicated)*
 * *LDR (predicate): Load predicate register*
 * *STR (predicate): Store predicate register*

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D146311