[all-commits] [llvm/llvm-project] a37df8: [SelectionDAG][RISCV] Remove code for handling too...

Craig Topper via All-commits all-commits at lists.llvm.org
Tue Mar 21 11:12:49 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a37df84f99ebe68c3e9cc533ffd3952fb22d1f38
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-03-21 (Tue, 21 Mar 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    A llvm/test/CodeGen/RISCV/rvv/pr61561.ll

  Log Message:
  [SelectionDAG][RISCV] Remove code for handling too small shift type from SimplifyDemandedBits.

This code detected that the type returned from getShiftAmountTy was
too small to hold the constant shift amount. But it used the full
type size instead of scalar type size leading it to crash for
scalable vectors.

This code was necessary when getShiftAmountTy would always
return the target preferred shift amount type for scalars even when
the type was an illegal type larger than the target supported. For
vectors, getShiftAmountTy has always returned the vector type.

Fortunately, getShiftAmountTy was fixed a while ago to detect that
the target's preferred size for scalars is not large enough for the
type. So we can delete this code.

Switched to use getShiftAmountConstant to further simplify the code.

Fixs PR61561.

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