[all-commits] [llvm/llvm-project] e7c1b4: [SystemZ] Fix modelling of composed subreg indices.

Carl Ritson via All-commits all-commits at lists.llvm.org
Tue Mar 21 08:40:53 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e7c1b4b64c314c9adb39857d92a660557217cada
  Author: Carl Ritson <carl.ritson at amd.com>
  Date:   2023-03-21 (Tue, 21 Mar 2023)

  Changed paths:
    M llvm/lib/Target/SystemZ/SystemZInstrFP.td
    M llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
    M llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
    M llvm/lib/Target/SystemZ/SystemZRegisterInfo.td
    M llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
    M llvm/test/CodeGen/SystemZ/cond-move-05.mir
    M llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir

  Log Message:
  [SystemZ] Fix modelling of composed subreg indices.

A rare case where coalescing resulted in a hh32 (high32 of high64 of vector
register) subreg usage caused getSubReg() to fail as the vector reg does not
have that subreg in its subregs list, but rather h32 which was expected to
also act as hh32. See link below for the discussion when solving this.

Patch By: critson

Reviewed By: uweigand

Fixes: https://github.com/llvm/llvm-project/issues/61390

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