[all-commits] [llvm/llvm-project] b688b5: [clang-format] Fix non-case colons in Verilog case...

[eywdck2l via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b688b58f83ceb48dbe185be95372e45de1d51401
      https://github.com/llvm/llvm-project/commit/b688b58f83ceb48dbe185be95372e45de1d51401
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2023-03-19 (Sun, 19 Mar 2023)

  Changed paths:
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp

  Log Message:
  -----------
  [clang-format] Fix non-case colons in Verilog case lines

Back in D128714, we should have replaced the old rule about colons when
we added the new one.  Because we didn't, all colons got mistaken as
case colons as long as the line began with `case` or `default`.  Now we
remove the rule that we forgot to remove.

Reviewed By: MyDeveloperDay, rymiel

Differential Revision: https://reviews.llvm.org/D145888