[all-commits] [llvm/llvm-project] 22c3ba: [SVE] Add patterns for shift intrinsics with False...

[lizhijin1024 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 22c3ba4bb519e12395c676ffe436ea4b8400234a
      https://github.com/llvm/llvm-project/commit/22c3ba4bb519e12395c676ffe436ea4b8400234a
  Author: lizhijin <lizhijin3 at huawei.com>
  Date:   2023-03-19 (Sun, 19 Mar 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm-zero.ll

  Log Message:
  -----------
  [SVE] Add patterns for shift intrinsics with FalseLanesZero mode

This patch adds patterns to reduce redundant mov and sel instructions
for shift intrinsics with FalseLanesZero mode, when
FeatureExperimentalZeroingPseudosis supported.

For example, before:

mov     z1.b, #0
sel     z0.b, p0, z0.b, z1.b
asr     z0.b, p0/m, z0.b, #7
After:

movprfx z0.b, p0/z, z0.b
asr     z0.b, p0/m, z0.b, #7

Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D145551