[all-commits] [llvm/llvm-project] 4e4af1: [mlir][gpu][nvvm] fixed bug with literal for inlin...

[Aart Bik via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4e4af1338da5bdbf10e113c0462d7eb7222b5d97
      https://github.com/llvm/llvm-project/commit/4e4af1338da5bdbf10e113c0462d7eb7222b5d97
  Author: Aart Bik <ajcbik at google.com>
  Date:   2023-03-17 (Fri, 17 Mar 2023)

  Changed paths:
    M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
    M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir

  Log Message:
  -----------
  [mlir][gpu][nvvm] fixed bug with literal for inline asm for mma instruction

The 'mma.sp.sync.aligned' family of instructions expects
the sparsity selector as a direct literal (0x0 or 0x1).
The current MLIR inline asm passed this as a value in
register, which broke the downstream assemblers

This is a small step towards supporting 2:4 sparsity on
NVidia GPUs in the sparse compiler of MLIR.

Reviewed By: ThomasRaoux, guraypp

Differential Revision: https://reviews.llvm.org/D146110