[all-commits] [llvm/llvm-project] 406336: [RISCV] Add MULW to RISCVStripWSuffix.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4063369fd452b9bb9941494023eea6395a1872d3
      https://github.com/llvm/llvm-project/commit/4063369fd452b9bb9941494023eea6395a1872d3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-03-16 (Thu, 16 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVStripWSuffix.cpp
    M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
    M llvm/test/CodeGen/RISCV/bitextract-mac.ll
    M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/machine-combiner.ll
    M llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
    M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
    M llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
    M llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/sextw-removal.ll
    M llvm/test/CodeGen/RISCV/srem-lkk.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
    M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/urem-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/usub_sat_plus.ll

  Log Message:
  -----------
  [RISCV] Add MULW to RISCVStripWSuffix.

This converts MULW to MUL if the upper bits aren't used.
This will give more opportunities to use c.mul with Zcb.