[all-commits] [llvm/llvm-project] acc03a: [RISCV] Enable interleaved access vectorization

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: acc03ad10af4f379a644e3956cb9aca54e40696c
      https://github.com/llvm/llvm-project/commit/acc03ad10af4f379a644e3956cb9aca54e40696c
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-03-15 (Wed, 15 Mar 2023)

  Changed paths:
    M llvm/include/llvm/IR/Instructions.h
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
    A llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/zvl32b.ll

  Log Message:
  -----------
  [RISCV] Enable interleaved access vectorization

The loop vectorizer supports generating interleaved loads and stores via
shuffle patterns for fixed length vectors.
This enables it for RISC-V, since interleaved shuffle patterns can be
lowered to vlseg/vsseg in https://reviews.llvm.org/D145022

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D145155