[all-commits] [llvm/llvm-project] 93b89b: [AArch64][SVE] Fix the indexed addressing mode whe...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 93b89bee471f58d798cba42d21201e154778846a
      https://github.com/llvm/llvm-project/commit/93b89bee471f58d798cba42d21201e154778846a
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2023-03-15 (Wed, 15 Mar 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll

  Log Message:
  -----------
  [AArch64][SVE] Fix the indexed addressing mode when FI = 0.

This is an alternative fix to D145497, which also addresses
  https://github.com/llvm/llvm-project/issues/60918

In D124457 which added the original code for this, @efriedma pointed
out that it wasn't safe to assume that FI #0 would be allocated at offset
0, but that part of the patch went in without any changes.

The downside of this solution is that any access to an object on the
stack that has been allocated at SP + 0, still gets moved to a separate
register first, which degrades performance.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D146056