[all-commits] [llvm/llvm-project] a1f8ba: [clang-format] Recognize Verilog always blocks

[eywdck2l via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a1f8bab9bad7dc7ef5bae518bc3289f4111846f3
      https://github.com/llvm/llvm-project/commit/a1f8bab9bad7dc7ef5bae518bc3289f4111846f3
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2023-03-14 (Tue, 14 Mar 2023)

  Changed paths:
    M clang/lib/Format/FormatToken.h
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/lib/Format/UnwrappedLineParser.cpp
    M clang/lib/Format/UnwrappedLineParser.h
    M clang/unittests/Format/FormatTestVerilog.cpp

  Log Message:
  -----------
  [clang-format] Recognize Verilog always blocks

The small `Coverage` test was added because we added the space rule
about 2 at signs along with the rule about only 1 of it. We have not
fully covered covergroup yet.

Reviewed By: MyDeveloperDay, owenpan

Differential Revision: https://reviews.llvm.org/D145794