[all-commits] [llvm/llvm-project] c7d844: [DAG] Use ISD::isBitwiseLogicOp in AND/OR/XOR chec...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c7d844ea0fae1e135028755de071a8c63ab6431a
      https://github.com/llvm/llvm-project/commit/c7d844ea0fae1e135028755de071a8c63ab6431a
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-03-13 (Mon, 13 Mar 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
    M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

  Log Message:
  -----------
  [DAG] Use ISD::isBitwiseLogicOp in AND/OR/XOR checks. NFCI.

There's additional cases we can cleanup (mainly in target code), but this tries to cleanup generic code and PPC which had an equivalent helper.