[all-commits] [llvm/llvm-project] c0c4c7: [RISCV] Return false for unsupported VTs in isFPIm...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c0c4c725e98c7339d8dbc8eec2a773d26f87929b
      https://github.com/llvm/llvm-project/commit/c0c4c725e98c7339d8dbc8eec2a773d26f87929b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-03-12 (Sun, 12 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Return false for unsupported VTs in isFPImmLegal.

I don't have a test case that fails for this, but it seemed like
we should only handle legal types. The callers I looked at in
DAGCombine either check the type is legal or don't even call
isFPImmLegal unless LegalOperations is true.

Written in a slightly odd way because switches on EVT require
an additional isSimple check so an if/else chain is easier. Used a bool
to shorten the code instead of having multiple ifs and returns.
AArch64 uses a similarish structure.