[all-commits] [llvm/llvm-project] 4d96a6: [AArch64] Fix N2 SchedModel for arithmetic and log...

[Ricardo Jesus via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4d96a6b7be08e63576af1b3c177a9a24795bae88
      https://github.com/llvm/llvm-project/commit/4d96a6b7be08e63576af1b3c177a9a24795bae88
  Author: Ricardo Jesus <rjj at nvidia.com>
  Date:   2023-03-10 (Fri, 10 Mar 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
    A llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s

  Log Message:
  -----------
  [AArch64] Fix N2 SchedModel for arithmetic and logic ops with cheap LSL

According to the N2 Software Optimization Guide, arithmetic ops with LSL
≤ 4, no flagset logical ops, and flagset logical ops with LSL = 0 have a
latency of 1 and use pipeline group I. However, most of these ops were
being modelled as having a latency of 2 and using pipeline M. The
affected instructions include the "unshifted" versions of ADD/SUB, among
others.

Differential Revision: https://reviews.llvm.org/D145370