[all-commits] [llvm/llvm-project] 865fb2: [RISCV] Pre-commit test case for D140460

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 865fb2e44011c60d6d69154d205b55f4b44ff10b
      https://github.com/llvm/llvm-project/commit/865fb2e44011c60d6d69154d205b55f4b44ff10b
  Author: Jim Lin <jim at andestech.com>
  Date:   2023-03-10 (Fri, 10 Mar 2023)

  Changed paths:
    A llvm/test/CodeGen/RISCV/stack-slot-coloring.mir

  Log Message:
  -----------
  [RISCV] Pre-commit test case for D140460

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D145549


  Commit: 7e9293572d332b812eb1e521f0a75a4e7034abbf
      https://github.com/llvm/llvm-project/commit/7e9293572d332b812eb1e521f0a75a4e7034abbf
  Author: Jim Lin <jim at andestech.com>
  Date:   2023-03-10 (Fri, 10 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/test/CodeGen/RISCV/stack-slot-coloring.mir

  Log Message:
  -----------
  [RISCV] Set how many bytes load from or store to stack slot

Refer from: https://reviews.llvm.org/D44782

After https://reviews.llvm.org/D130302, LW+SEXT.B can be folded into LB
as partially reload stack slot. This gains incorrect optimization result
from `StackSlotColoring` without given the number of bytes exactly load
from stack. LB+SW are mis-interpreted as fully reload/restore from stack
slot without the sign-extension. SW would be considered as a redundant store.

The testcase is copied from llvm/test/CodeGen/X86/pr30821.mir.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D145471


Compare: https://github.com/llvm/llvm-project/compare/bb01b9919fdd...7e9293572d33