[all-commits] [llvm/llvm-project] d610c6: [RISCV] Add vsseg intrinsic for fixed length vectors

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d610c6c9c73576a8afb9831a0c6e8fc675c2a6e6
      https://github.com/llvm/llvm-project/commit/d610c6c9c73576a8afb9831a0c6e8fc675c2a6e6
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-03-08 (Wed, 08 Mar 2023)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-store.ll

  Log Message:
  -----------
  [RISCV] Add vsseg intrinsic for fixed length vectors

These intrinsics are equivalent to the regular @llvm.riscv.vssegNF
intrinsics, only they accept fixed length vectors in their overloaded
types: The regular intrinsics only operate on scalable vectors.
These intrinsics convert the fixed length vectors to scalable ones, and
then lower it on to the regular scalable intrinsic.

This mirrors the intrinsics added in 0803dba7dd998ad073d75a32b65296734c10ae70
This will be used in a later patch with the Interleaved Access pass.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D145022