[all-commits] [llvm/llvm-project] 3b1240: [RISCV] Add classes to define SchedWrite list

Wang Pengcheng via All-commits all-commits at lists.llvm.org
Tue Mar 7 01:54:53 PST 2023


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3b1240ea763d8c4a536af713ae1e6aad9c1f4da3
      https://github.com/llvm/llvm-project/commit/3b1240ea763d8c4a536af713ae1e6aad9c1f4da3
  Author: wangpc <pc.wang at linux.alibaba.com>
  Date:   2023-03-07 (Tue, 07 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Add classes to define SchedWrite list

SchedWrites are relevant to LMUL for most instructions, so we have
to enumerate all defined SchedWrites when defining ReadAdcance.
This patch adds some classes to simplify these definitions.

Reviewed By: michaelmaitland

Differential Revision: https://reviews.llvm.org/D145041


  Commit: 5fdab3c81bb2b702549d3e7c30f8cc66ea86c4dd
      https://github.com/llvm/llvm-project/commit/5fdab3c81bb2b702549d3e7c30f8cc66ea86c4dd
  Author: wangpc <pc.wang at linux.alibaba.com>
  Date:   2023-03-07 (Tue, 07 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    A llvm/test/CodeGen/RISCV/copyprop.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    M llvm/test/CodeGen/RISCV/sadd_sat.ll
    M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
    M llvm/test/CodeGen/RISCV/split-offsets.ll
    M llvm/test/CodeGen/RISCV/ssub_sat.ll
    M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
    M llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution.ll

  Log Message:
  -----------
  [RISCV] Enable machine copy propagation for copy-like instructions

Like what has been done in AArch64 (D125335).

We enable this under `-O2` to show the codegen diffs here but we
may only do this under `-O3` like AArch64.

There are two cases that we may produce these eliminable copies:
1. ISel of `FrameIndex`. Like `rvv/fixed-vectors-calling-conv.ll`.
2. Tail duplication. Like `select-optimize-multiple.ll`.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144535


Compare: https://github.com/llvm/llvm-project/compare/fb309041f0c3...5fdab3c81bb2


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