[all-commits] [llvm/llvm-project] ada264: [RISCV][CodeGen] Add codegen pattern for FLI instr...

[joshua-arch1 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ada2641460672ed888df9e2791d3d4635f06e2ae
      https://github.com/llvm/llvm-project/commit/ada2641460672ed888df9e2791d3d4635f06e2ae
  Author: Jun Sha (Joshua) <cooper.joshua at linux.alibaba.com>
  Date:   2023-03-07 (Tue, 07 Mar 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
    M llvm/test/CodeGen/RISCV/double-zfa.ll
    M llvm/test/CodeGen/RISCV/float-zfa.ll
    M llvm/test/CodeGen/RISCV/half-zfa.ll

  Log Message:
  -----------
  [RISCV][CodeGen] Add codegen pattern for FLI instruction in experimental zfa extension

This patch implements experimental support for the RISCV Zfa extension as specified here: https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf, Ch. 25. This extension has not been ratified. Once ratified, it'll move out of experimental status.

This change adds codegen support for load-immediate instructions (fli.s/fli.d/fli.h).

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D141560