[all-commits] [llvm/llvm-project] a10ac6: [AArch64] Extend load insert into zero patterns to...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a10ac6554db4dee93232139d5c29f8d91ee01f3b
      https://github.com/llvm/llvm-project/commit/a10ac6554db4dee93232139d5c29f8d91ee01f3b
  Author: David Green <david.green at arm.com>
  Date:   2023-03-06 (Mon, 06 Mar 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/load-insert-zero.ll

  Log Message:
  -----------
  [AArch64] Extend load insert into zero patterns to SVE.

This extends the patterns for loading into the zeroth lane of a zero vector
from D144086 to SVE, which work in the same way as the existing patterns. Only
full length vectors are added here, not the narrower floating point vector
types.