[all-commits] [llvm/llvm-project] 204800: [IR][Legalization] Promote illegal deinterleave an...

[CarolineConcatto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 204800ad0aa2cdf3be43c76375336cee47dca004
      https://github.com/llvm/llvm-project/commit/204800ad0aa2cdf3be43c76375336cee47dca004
  Author: Caroline Concatto <caroline.concatto at arm.com>
  Date:   2023-03-03 (Fri, 03 Mar 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll
    M llvm/test/CodeGen/AArch64/sve-vector-interleave.ll

  Log Message:
  -----------
  [IR][Legalization] Promote illegal deinterleave and interleave vectors

To make legalization easier, the operands and outputs have the same size for
these ISD Nodes. When legalizing the results in PromoteIntegerResult the operands
are legalized to the same size as the outputs.
The ISD Node has two output/results, therefore the legalizing functions update
both results/outputs.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D144846