[all-commits] [llvm/llvm-project] 83bbd3: [AArch64] Load into zero vector patterns

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 83bbd3fdbd75295669cf97967c38810d427c5c25
      https://github.com/llvm/llvm-project/commit/83bbd3fdbd75295669cf97967c38810d427c5c25
  Author: David Green <david.green at arm.com>
  Date:   2023-03-01 (Wed, 01 Mar 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/load-insert-zero.ll
    M llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll

  Log Message:
  -----------
  [AArch64] Load into zero vector patterns

A LDR will implicitly zero the rest of the vector, so vector_insert(zeros,
load, 0) can use a single load. This adds tablegen patterns for both scaled and
unscaled loads, detecting where we are inserting a load into the lower element
of a zero vector.

Differential Revision: https://reviews.llvm.org/D144086