[all-commits] [llvm/llvm-project] 18af85: [AArch64] Remove 64bit->128bit vector insert lowering

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 18af85302200580ca4fc54bfee2a8a0ec2c8d7b9
      https://github.com/llvm/llvm-project/commit/18af85302200580ca4fc54bfee2a8a0ec2c8d7b9
  Author: David Green <david.green at arm.com>
  Date:   2023-03-01 (Wed, 01 Mar 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll
    M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll

  Log Message:
  -----------
  [AArch64] Remove 64bit->128bit vector insert lowering

The AArch64 backend, during lowering, will convert an 64bit vector insert to a
128bit vector:

vector_insert %dreg, %v, %idx
=>
%qreg = insert_subvector undef, %dreg, 0
%ins = vector_insert %qreg, %v, %idx
EXTRACT_SUBREG %ins, dsub

This creates a bit of mess in the DAG, and the EXTRACT_SUBREG being a machine
nodes makes it difficult to simplify. This patch removes that, treating the
64bit vector insert as legal and handling them with extra tablegen patterns.

The end result is a simpler DAG that is easier to write tablegen patterns for.

Differential Revision: https://reviews.llvm.org/D144550