[all-commits] [llvm/llvm-project] 31d6a5: [AArch64][GlobalISel] Reorder stack up-adjustment ...

[Amara Emerson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 31d6a572579a5d1d9ae14a1a9d4ffbdb1b098e49
      https://github.com/llvm/llvm-project/commit/31d6a572579a5d1d9ae14a1a9d4ffbdb1b098e49
  Author: Amara Emerson <amara at apple.com>
  Date:   2023-02-27 (Mon, 27 Feb 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-log.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir
    A llvm/test/CodeGen/AArch64/aarch64-fastcc-stackup.ll
    M llvm/test/CodeGen/AArch64/arm64-this-return.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Reorder stack up-adjustment and register copies

This change reorders the stack up-adjustment and return value copying phases of
machine-ir generation on Aarch64. Doing so prevents a bug observed for fastcc
calls with >8 arguments, where the up-adjustment required from making that call
is placed in the wrong place relative to spill and reloading code.

See: https://github.com/llvm/llvm-project/issues/60972 for full issue
reproduction and context.

Patch contributed by Bruce Collie

Differential Revision: https://reviews.llvm.org/D144791