[all-commits] [llvm/llvm-project] 7ae071: Add more tests for promoting `blendw` -> `blendd`; ...

[goldsteinn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7ae071f98186751627effeede9beba9df78f04ea
      https://github.com/llvm/llvm-project/commit/7ae071f98186751627effeede9beba9df78f04ea
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-26 (Sun, 26 Feb 2023)

  Changed paths:
    A llvm/test/CodeGen/X86/shuffle-blendw.ll

  Log Message:
  -----------
  Add more tests for promoting `blendw` -> `blendd`; NFC

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D143788


  Commit: 6b6c62c75b8b5047a0def2dedcadd367a88e7002
      https://github.com/llvm/llvm-project/commit/6b6c62c75b8b5047a0def2dedcadd367a88e7002
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-26 (Sun, 26 Feb 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/combine-sdiv.ll
    M llvm/test/CodeGen/X86/shuffle-blendw.ll

  Log Message:
  -----------
  Widen i16 shuffle masks if vector width < 512 even with BWI

`{v}blend{d|ps|pd}` is preferable to `{v}blendw` so widen so that we
can match it.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D143789


  Commit: d821ac1aaf94091c03314c8ba03d6b64c0309038
      https://github.com/llvm/llvm-project/commit/d821ac1aaf94091c03314c8ba03d6b64c0309038
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-26 (Sun, 26 Feb 2023)

  Changed paths:
    A llvm/test/CodeGen/X86/combine-mask-with-shuffle.ll

  Log Message:
  -----------
  Add tests for combining mask with shuffles; NFC

Differential Revision: https://reviews.llvm.org/D144144


  Commit: b5fc2a474ebabb082f52f43cea2d5b299f28bd70
      https://github.com/llvm/llvm-project/commit/b5fc2a474ebabb082f52f43cea2d5b299f28bd70
  Author: Noah Goldstein <goldstein.w.n at gmail.com>
  Date:   2023-02-26 (Sun, 26 Feb 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/combine-mask-with-shuffle.ll
    M llvm/test/CodeGen/X86/vselect-avx512.ll

  Log Message:
  -----------
  Add additional operations that masked instructions can combine with

Added: OR, SMAX, SMIN, UMAX, UMIN, ABS, SHL, SRL, SRA, MUL

Intentionally not generically using TLI.isBinOp as that causes
regressions as there are many binops that cannot combine with masked
instructions.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D143860


Compare: https://github.com/llvm/llvm-project/compare/d91c20a0de70...b5fc2a474eba