[all-commits] [llvm/llvm-project] 893428: [RISCV] Add explicit types to some XTHead isel pat...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 893428767cbef85b0c729d3f0d36ab717c950bcf
      https://github.com/llvm/llvm-project/commit/893428767cbef85b0c729d3f0d36ab717c950bcf
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-25 (Sat, 25 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

  Log Message:
  -----------
  [RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel.inc size.

HWMode expansion of GPR can create patterns with i32 types with
Subtarget->is64Bit() or i64 types with !Subtarget->is64Bit().
These patterns will never match. They just waste space in the table.

By adding explicit i32 or i64 to patterns that only apply to RV32
or RV64 we can filter these patterns.