[all-commits] [llvm/llvm-project] f07bb0: foo

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f07bb0012e76495d50b34fe50fe7d41a70c8685b
      https://github.com/llvm/llvm-project/commit/f07bb0012e76495d50b34fe50fe7d41a70c8685b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-25 (Sat, 25 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

  Log Message:
  -----------
  foo


  Commit: 7910ed1d56c349b76c82d5ebe2f2590770955ff5
      https://github.com/llvm/llvm-project/commit/7910ed1d56c349b76c82d5ebe2f2590770955ff5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-25 (Sat, 25 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

  Log Message:
  -----------
  [RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel.inc size.

HWMode expansion of GPR can create patterns with i32 types with
Subtarget->is64Bit() or i64 types with !Subtarget->is64Bit().
These patterns will never match. They just waste space in the table.

By adding explicit i32 or i64 to patterns that only apply to RV32
or RV64 we can filter these patterns.


Compare: https://github.com/llvm/llvm-project/compare/80ddb9c2a79d...7910ed1d56c3