[all-commits] [llvm/llvm-project] f68f04: [RISCV] Add vendor-defined XTheadCondMov (conditio...

[Philipp Tomsich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f68f04d07c69049a95a5f43b5d001ee5a2c87338
      https://github.com/llvm/llvm-project/commit/f68f04d07c69049a95a5f43b5d001ee5a2c87338
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2023-02-24 (Fri, 24 Feb 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    A llvm/test/CodeGen/RISCV/condops.ll
    R llvm/test/CodeGen/RISCV/xventanacondops.ll
    A llvm/test/MC/RISCV/xtheadcondmov-invalid.s
    A llvm/test/MC/RISCV/xtheadcondmov-valid.s

  Log Message:
  -----------
  [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension

The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
instructions with $rd being an input and an ouput instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144681