[all-commits] [llvm/llvm-project] 7b79e8: [RISCV] Add vendor-defined XTheadFMemIdx (FP Index...

[Philipp Tomsich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7b79e8d45576e17daca4853deae40119615588b0
      https://github.com/llvm/llvm-project/commit/7b79e8d45576e17daca4853deae40119615588b0
  Author: Manolis Tsamis <manolis.tsamis at vrull.eu>
  Date:   2023-02-24 (Fri, 24 Feb 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    A llvm/test/CodeGen/RISCV/xtheadfmemidx.ll
    A llvm/test/MC/RISCV/rv32xtheadfmemidx-d-invalid.s
    A llvm/test/MC/RISCV/rv32xtheadfmemidx-f-invalid.s
    A llvm/test/MC/RISCV/rv32xtheadfmemidx-valid.s
    A llvm/test/MC/RISCV/rv64xtheadfmemidx-invalid.s
    A llvm/test/MC/RISCV/rv64xtheadfmemidx-valid.s

  Log Message:
  -----------
  [RISCV] Add vendor-defined XTheadFMemIdx (FP Indexed Memory Operations) extension

The vendor-defined XTHeadFMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
for floating-point registers.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=f511f80fa3fcaf6bcbe727fb902b8bd5ec8f9c20

Depends on D144249

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144647