[all-commits] [llvm/llvm-project] 230e61: [LegalizeTypes] Add a special case for (add X, 1) ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 230e61658b5e5c91f631459511f0efb4b15f8c77
      https://github.com/llvm/llvm-project/commit/230e61658b5e5c91f631459511f0efb4b15f8c77
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-23 (Thu, 23 Feb 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
    M llvm/test/CodeGen/RISCV/branch-on-zero.ll
    M llvm/test/CodeGen/RISCV/forced-atomics.ll
    M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll

  Log Message:
  -----------
  [LegalizeTypes] Add a special case for (add X, 1) to ExpandIntRes_ADDSUB.

On targets without ADDCARRY or ADDE, we need to emit a separate
SETCC to determine carry from the low half to the high half. Usually
we do (setult Lo, LHSLo). If RHSLo is 1 we can instead do (seteq Lo, 0).
This can reduce the live range of LHSLo.