[all-commits] [llvm/llvm-project] 8d15e7: [RISCV] Lower interleave and deinterleave intrinsics

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8d15e7275fe104520af0805b432681445c5196ea
      https://github.com/llvm/llvm-project/commit/8d15e7275fe104520af0805b432681445c5196ea
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-02-23 (Thu, 23 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    A llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
    A llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    A llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
    A llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

  Log Message:
  -----------
  [RISCV] Lower interleave and deinterleave intrinsics

Lower the two intrinsics introduced in D141924.

These intrinsics can be combined with loads and stores into the much more efficient segmented load and store instructions in a following patch.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D144092


  Commit: e340e9e632124f541d8225ccf0a5c55de402fb3c
      https://github.com/llvm/llvm-project/commit/e340e9e632124f541d8225ccf0a5c55de402fb3c
  Author: Luke Lau <luke at igalia.com>
  Date:   2023-02-23 (Thu, 23 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV][NFC] Reuse getDeinterleaveViaVNSRL to lower deinterleave intrinsics

This modifies it to work on both scalable and fixed vectors

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D144584


Compare: https://github.com/llvm/llvm-project/compare/25d23b1970ea...e340e9e63212