[all-commits] [llvm/llvm-project] b3dc0e: [AMDGPU][MC][GFX11] Add Partial NSA format for ima...

[Mirko Brkušanin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b3dc0e69cf3b7778987565ba5ff03dba3b9b8c48
      https://github.com/llvm/llvm-project/commit/b3dc0e69cf3b7778987565ba5ff03dba3b9b8c48
  Author: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
  Date:   2023-02-23 (Thu, 23 Feb 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    M llvm/lib/Target/AMDGPU/GCNSubtarget.h
    M llvm/lib/Target/AMDGPU/MIMGInstructions.td
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
    M llvm/test/MC/AMDGPU/gfx11_asm_mimg_features.s
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt

  Log Message:
  -----------
  [AMDGPU][MC][GFX11] Add Partial NSA format for image sample instructions

Image sample instructions that need more than 5 VGPRs for VAddr can use
partial NSA for NSA encoding format. VGPRs that can not fit into the
encoding are sequential after the last one.
This patch adds assembly and disassembly parts.

Differential Revision: https://reviews.llvm.org/D144033


  Commit: 926746d22abd08490923e197279bc86d5b32db67
      https://github.com/llvm/llvm-project/commit/926746d22abd08490923e197279bc86d5b32db67
  Author: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
  Date:   2023-02-23 (Thu, 23 Feb 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
    A llvm/test/CodeGen/AMDGPU/verify-image-partial-nsa.mir

  Log Message:
  -----------
  [AMDGPU][GFX11] Legalize and select partial NSA MIMG instructions

If more registers are needed for VAddr then the NSA format allows then the
final register can act as a contigous set of remaining addresses. Update
legalizer to pack register for this new format and allow instruction
selection to use NSA encoding when number of addresses exceeds max size.
Also update SIShrinkInstructions to handle partial NSA.

Differential Revision: https://reviews.llvm.org/D144034


Compare: https://github.com/llvm/llvm-project/compare/51a49ec52a08...926746d22abd