[all-commits] [llvm/llvm-project] 3b8c0b: [RISCV] Add new pass to transform undef to pseudo ...

Piyou Chen via All-commits all-commits at lists.llvm.org
Wed Feb 22 04:33:52 PST 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3b8c0b342e16e9df74ed26b96b18b0a623896004
  Author: Piyou Chen <piyou.chen at sifive.com>
  Date:   2023-02-22 (Wed, 22 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/CMakeLists.txt
    M llvm/lib/Target/RISCV/RISCV.h
    M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
    M llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll

  Log Message:
  [RISCV] Add new pass to transform undef to pseudo for vector values.

RISC-V vector instruction has register overlapping constraint for certain
instructions, and will cause illegal instruction trap if violated, we use
early clobber to model this constraint, but it can't prevent register allocator
allocated same or overlapped if the input register is undef value, so convert
IMPLICIT_DEF to temporary pseudo could prevent that happen, it's not best way
to resolve this. Ideally we should model the constraint right, but before we
model the constraint right, it's the approach to prevent that happen.

See also: https://github.com/llvm/llvm-project/issues/50157

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D129735

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