[all-commits] [llvm/llvm-project] 6e473a: [clang-format] Put ports on separate lines in Veri...

[eywdck2l via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6e473aeffdc1c26307e19f68252767a32e0047ad
      https://github.com/llvm/llvm-project/commit/6e473aeffdc1c26307e19f68252767a32e0047ad
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2023-02-20 (Mon, 20 Feb 2023)

  Changed paths:
    M clang/lib/Format/FormatToken.h
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp

  Log Message:
  -----------
  [clang-format] Put ports on separate lines in Verilog module headers

New:
```
module mh1
    (input var int in1,
     input var in2, in3,
     output tagged_st out);
endmodule
```

Old:
```
module mh1
    (input var int in1, input var in2, in3, output tagged_st out);
endmodule
```

`getNextNonComment` was modified to return a non-const pointer because
we needed to use it that way in `verilogGroupDecl`.

The comment on line 2626 was a typo.  We corrected it while modifying
the function.

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D143825