[all-commits] [llvm/llvm-project] 78f106: [RISCV] Handle RISCVISD::SplitF64 and RISCVISD::Bu...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 78f106a554b0c3ee8468ce291b5df5a730207490
      https://github.com/llvm/llvm-project/commit/78f106a554b0c3ee8468ce291b5df5a730207490
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-18 (Sat, 18 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

  Log Message:
  -----------
  [RISCV] Handle RISCVISD::SplitF64 and RISCVISD::BuildPairF64 during isel with Zfa.

Instead of special casing Zfa in the custom inserters, select the
correct instructions during isel.

BuildPairF64 we can do with pattern, but SplitF64 requires custom
selection due to the two destinations.

If we didn't need SplitF64 without Zfa, I would have an extract low
and extract high ISD opcode for Zfa to avoid that issue.