[all-commits] [llvm/llvm-project] 42944a: [RISCV] Improve isInterleaveShuffle to handle inte...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 42944abf8583fc6efae5bbc39f092bf884f6d17c
      https://github.com/llvm/llvm-project/commit/42944abf8583fc6efae5bbc39f092bf884f6d17c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-02-17 (Fri, 17 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll

  Log Message:
  -----------
  [RISCV] Improve isInterleaveShuffle to handle interleaving the high half and low half of the same source.

This is needed to support the new interleave intrinsics from D141924 for
fixed vectors.

I've reworked the core loop to operate in terms of half of a source. Making 4
possible half sources. The first element of the half is used to indicate which
source using the same numbering as the shuffle where the second source elements
are numbered after the first source.

I've added restrictions to only match the first half of two vectors or the
first and second half of a single vector. This was done to prevent regressions
on the cases we have coverage for. I saw cases where generic DAG combine split
a single interleave into 2 smaller interleaves a concat. We can revisit in the
future.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D144143