[all-commits] [llvm/llvm-project] f6fa5a: [RISCV][MC] Add support for experimental zfa exten...

[joshua-arch1 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f6fa5a66d8a8190002d3eb542e4b5a99deb53004
      https://github.com/llvm/llvm-project/commit/f6fa5a66d8a8190002d3eb542e4b5a99deb53004
  Author: Jun Sha (Joshua) <cooper.joshua at linux.alibaba.com>
  Date:   2023-02-16 (Thu, 16 Feb 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
    A llvm/test/MC/RISCV/rv32zfa-only-valid.s
    A llvm/test/MC/RISCV/zfa-double-invalid.s
    A llvm/test/MC/RISCV/zfa-half-invalid.s
    A llvm/test/MC/RISCV/zfa-invalid.s
    A llvm/test/MC/RISCV/zfa-valid.s

  Log Message:
  -----------
  [RISCV][MC] Add support for experimental zfa extension (FLI instruction not included)

This implements experimental support for the RISCV Zfa extension as specified here: https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf, Ch. 25. This extension has not been ratified. Once ratified, it'll move out of experimental status.

This change adds assembly support for all instructions except load-immediate instructions (fli.s/fli.d/fli.h).  Assembly support for that instruction and codegen support will follow in separate patches.

Differential Revision: https://reviews.llvm.org/D141984