[all-commits] [llvm/llvm-project] 7e6e63: Use llvm::has_single_bit<uint32_t> (NFC)

[kazutakahirata via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7e6e636fb683a854de27f56b2da7d157a0b70f4e
      https://github.com/llvm/llvm-project/commit/7e6e636fb683a854de27f56b2da7d157a0b70f4e
  Author: Kazu Hirata <kazu at google.com>
  Date:   2023-02-15 (Wed, 15 Feb 2023)

  Changed paths:
    M clang/lib/CodeGen/CGNonTrivialStruct.cpp
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/AVR/AVRISelLowering.cpp
    M llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
    M llvm/utils/TableGen/DAGISelMatcherGen.cpp

  Log Message:
  -----------
  Use llvm::has_single_bit<uint32_t> (NFC)

This patch replaces isPowerOf2_32 with llvm::has_single_bit<uint32_t>
where the argument is wider than uint32_t.