[all-commits] [llvm/llvm-project] b0bfba: [AArch64] Always lower fp16 zero to FMOVH0

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b0bfbad19b0698c51a0b932f82f778e67f2d7e0c
      https://github.com/llvm/llvm-project/commit/b0bfbad19b0698c51a0b932f82f778e67f2d7e0c
  Author: David Green <david.green at arm.com>
  Date:   2023-02-15 (Wed, 15 Feb 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-fmax.ll
    M llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
    M llvm/test/CodeGen/AArch64/f16-imm.ll
    M llvm/test/CodeGen/AArch64/mattr-all.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fadd.ll

  Log Message:
  -----------
  [AArch64] Always lower fp16 zero to FMOVH0

We can always use FMOVH0 to lower fp16 zero, even without fullfp16. We can
either expand it to movi d0, #0 or fmov s0, wzr, which will both clear all the
bits of the register.

Differential Revision: https://reviews.llvm.org/D143988