[all-commits] [llvm/llvm-project] f3c008: DAG: Relax foldBitcastedFPLogic conditions

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f3c008ca776bd17c085ba5be34cdf7569971628a
      https://github.com/llvm/llvm-project/commit/f3c008ca776bd17c085ba5be34cdf7569971628a
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-02-14 (Tue, 14 Feb 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
    M llvm/test/CodeGen/AMDGPU/fneg.ll

  Log Message:
  -----------
  DAG: Relax foldBitcastedFPLogic conditions

Requiring a bitcast to exist was unhelpful. The most basic cases
are always going to be a CopyFromReg or load, so they would need
a new cast inserted. Don't require a bitcast if it's a free
operation. I don't think this logic makes particularly much sense
(it seems to be imparting special interpretation of bitcast), but
this needs to be in sync with foldSignChangeInBitcast.

We should also get rid of this hasBitPreservingFPLogic hook. fabs/fneg
are bitpreserving or incorrectly implemented, so this should just be a
regular legality check.