[all-commits] [llvm/llvm-project] 04a2ba: [RISCV] Add vendor-defined XTHeadBs (single-bit) e...

[Philipp Tomsich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 04a2baf58f2362cac85edbd55747cecb135b9ae5
      https://github.com/llvm/llvm-project/commit/04a2baf58f2362cac85edbd55747cecb135b9ae5
  Author: Philipp Tomsich <philipp.tomsich at vrull.eu>
  Date:   2023-02-13 (Mon, 13 Feb 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/bittest.ll
    A llvm/test/CodeGen/RISCV/rv32xtheadbs.ll
    A llvm/test/CodeGen/RISCV/rv64xtheadbs.ll
    A llvm/test/MC/RISCV/rv32xtheadbs-invalid.s
    A llvm/test/MC/RISCV/rv32xtheadbs-valid.s
    A llvm/test/MC/RISCV/rv64xtheadbs-invalid.s

  Log Message:
  -----------
  [RISCV] Add vendor-defined XTHeadBs (single-bit) extension

The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs.  It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBs is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143036