[all-commits] [llvm/llvm-project] b134c6: [AArch64] Fix creation of invalid instructions wit...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b134c62facef01dabf901ee6a6283e3b0fb3a249
      https://github.com/llvm/llvm-project/commit/b134c62facef01dabf901ee6a6283e3b0fb3a249
  Author: David Green <david.green at arm.com>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
    M llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir

  Log Message:
  -----------
  [AArch64] Fix creation of invalid instructions with XZR register

A combination of GlobalISel and MachineCombiner can end up creating
`SUB xrz, (MOVI -2105098)` instructions which have not been constant
folded. The AArch64MIPeepholeOpt pass will then attempt to create
`ADD xzr, 513, lsl 12`, which is not a valid instruction. This adds
a bail out of the transform if the register is xzr/wzr.

Fixes #60528

Differential Revision: https://reviews.llvm.org/D143475