[all-commits] [llvm/llvm-project] cde2f3: [AMDGPU] Introduce never uniform bit field in tabl...

[yashssh via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cde2f330b36fc36760329be1d3c52e92da400663
      https://github.com/llvm/llvm-project/commit/cde2f330b36fc36760329be1d3c52e92da400663
  Author: Yashwant Singh <Yashwant.Singh at amd.com>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIDefines.h
    M llvm/lib/Target/AMDGPU/SIInstrFormats.td
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/VOP2Instructions.td
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/always-uniform.mir
    M llvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/never-uniform.mir

  Log Message:
  -----------
  [AMDGPU] Introduce never uniform bit field in tablegen

IsNeverUniform can be set to 1 to mark instructions which are
inherently never-uniform/divergent. Enabling this bit in
Writelane instruction for now. To be extended to all required
instructions.

Reviewed By: arsenm, sameerds, #amdgpu

Differential Revision: https://reviews.llvm.org/D143154