[all-commits] [llvm/llvm-project] 781ded: [RISCV][CodeGen] Account for LMUL from VS2 for Vec...

[Monk Chiang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 781dedba3022c90bd64bd580a5d146d1eea794f4
      https://github.com/llvm/llvm-project/commit/781dedba3022c90bd64bd580a5d146d1eea794f4
  Author: Monk Chiang <monk.chiang at sifive.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV][CodeGen] Account for LMUL from VS2 for Vector Reduction Instructions

The Reduction instruction destination register LMUL is 1. But the source
register(vs2) has different LMUL(MF8 to M8). It's beneficial to know how
many registers are working on reduction instructions.
This patch creates separate SchedWrite for each relevant LMUL that from VS2.

Reviewed By: michaelmaitland

Differential Revision: https://reviews.llvm.org/D141565