[all-commits] [llvm/llvm-project] 90c98f: [AArch64][GlobalISel] Legalize wide s8/s16 vectors...

[Vladislav Dzhidzhoev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 90c98f8e5516901cd5dbd677e65fb8d7dd483cba
      https://github.com/llvm/llvm-project/commit/90c98f8e5516901cd5dbd677e65fb8d7dd483cba
  Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
  Date:   2023-02-07 (Tue, 07 Feb 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Legalize wide s8/s16 vectors G_ADD/G_MUL/G_OR/...

Clamp the max number of elements of s8/s16 vectors when legalizing G_ADD,
G_SUB, G_MUL, G_AND, G_OR, G_XOR, in order to support some wide vectors.

Fixes https://github.com/llvm/llvm-project/issues/58156.

Differential Revision: https://reviews.llvm.org/D143517