[all-commits] [llvm/llvm-project] c24b35: [TailDuplicator] Pre-commit test case for a subreg...
Björn Pettersson via All-commits
all-commits at lists.llvm.org
Mon Feb 6 10:23:26 PST 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: c24b35b8f71b636cf88ac082c580e7f6a9cc6e59
https://github.com/llvm/llvm-project/commit/c24b35b8f71b636cf88ac082c580e7f6a9cc6e59
Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2023-02-06 (Mon, 06 Feb 2023)
Changed paths:
A llvm/test/CodeGen/AArch64/taildup-subreg-compose.mir
Log Message:
-----------
[TailDuplicator] Pre-commit test case for a subreg composition bug
Differential Revision: https://reviews.llvm.org/D140495
Commit: df947febe2eebce4a1b244947dd8a02068edb306
https://github.com/llvm/llvm-project/commit/df947febe2eebce4a1b244947dd8a02068edb306
Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2023-02-06 (Mon, 06 Feb 2023)
Changed paths:
M llvm/lib/CodeGen/TailDuplicator.cpp
M llvm/test/CodeGen/AArch64/taildup-subreg-compose.mir
Log Message:
-----------
[TailDuplicator] Fix old bugs in TailDuplicator::duplicateInstruction
This patch is updating TailDuplicator::duplicateInstruction to fix
some old bugs that has been found with an out-of-tree target. There
are three different things being addressed:
1) In one situation two subregister indices are combined using the
composeSubRegIndices helper. But the order in which those indices
are combined has been incorrect. For this problem I managed to
create some kind of reproducer using AArch64 (see the test case
touched in this patch).
2) Another fault was found in the else branch for the above situation.
Here we do not compose the two subregisters, instead we insert a
COPY to replace the PHI, and then the subreg index in the using
MO remains. Thus, the virtual register created for the COPY should
always match with the size of the original register. Therefore the
optimization that "constrain" (or rather relax) the register
class by looking at the instruction desc must be limited to the
situation when there is no subregister access. Otherwise we create
a vreg with the wrong class.
3) Last problem addressed in this patch is that when a new register
class is picked by looking at the instruction desc, then it
isn't guaranteed that the isAllocatable property is set for that
class. So one need to use the getAllocatableClass helper to find
a subclass that is allocatable before using createVirualRegister,
or alternatively (as in this patch) just use the OrigRC instead
of relaxing the register class for the COPY destination.
Haven't been able to find any in-tree reproducers for problem 2 and 3.
The tricky part is to find a target that has register hierarchies that
match with the problem to trigger those code paths (and with subreg
accesses involved).
Differential Revision: https://reviews.llvm.org/D140496
Commit: 525ed98be483188db6dc3bb69cecd0123148ceca
https://github.com/llvm/llvm-project/commit/525ed98be483188db6dc3bb69cecd0123148ceca
Author: Bjorn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2023-02-06 (Mon, 06 Feb 2023)
Changed paths:
M llvm/lib/Analysis/Lint.cpp
Log Message:
-----------
[Lint] Use new PM instead of legacy PM in lintFunction and lintModule
There are some helpers in the Lint analysis pass that will setup
a pass manager and then run the Lint pass on a given Function/Module.
Those have been using the LegacyPassManager, but as a small step
towards removing the deprecated legacy pass manager this patch is
changing those helpers into using the new pass manager instead.
No idea if anyone is really is using those helpers. Maybe an
alternative had been to just remove them. There is at least no unit
tests or similar that verifies that they work, so I validated this
patch by using a hacked opt binary that called those functions
before running the normal pipeline.
Differential Revision: https://reviews.llvm.org/D143388
Compare: https://github.com/llvm/llvm-project/compare/2155195131a5...525ed98be483
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