[all-commits] [llvm/llvm-project] 505cf2: [X86] combineConcatVectorOps - merge 256-bit logic...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 505cf2b6a5f2b5d4aba449172283cbe2776662df
      https://github.com/llvm/llvm-project/commit/505cf2b6a5f2b5d4aba449172283cbe2776662df
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-02-06 (Mon, 06 Feb 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vector-fshl-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-256.ll

  Log Message:
  -----------
  [X86] combineConcatVectorOps - merge 256-bit logic ops on AVX2+

AVX1 doesn't benefit as nearly all integer ops will stay as 128-bit ops.

This only exposes a couple of minor changes but will be a lot more useful in an upcoming shuffle combining patch.


  Commit: 2cf31ba5dccecd48d5f3c9d9d5c3808a144a7e6e
      https://github.com/llvm/llvm-project/commit/2cf31ba5dccecd48d5f3c9d9d5c3808a144a7e6e
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-02-06 (Mon, 06 Feb 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll

  Log Message:
  -----------
  [X86] combineConcatVectorOps - add X86ISD::VPERMV handling


Compare: https://github.com/llvm/llvm-project/compare/5de5f66b984a...2cf31ba5dcce